Established silicon dry etching recipes simply cannot be directly applied to silicon carbide (SiC) etching. SiC exhibits fundamentally different material properties from silicon—such as strong chemical bonding, high thermal conductivity, and extreme hardness—which fundamentally change how the material reacts within plasma.

Market Drivers for SiC Power Devices and the Mounting Pressure on Fabrication Processes

Silicon carbide (SiC) semiconductors are increasingly being adopted as next-generation devices that outperform conventional silicon in power conversion efficiency. This surging demand is driven primarily by electric vehicles (EVs), renewable energy infrastructure, and the recent rapid expansion of AI data centers.
Market research indicates that the rollout of 800V battery electric vehicles (BEVs)—which require significantly more SiC content than lower-voltage models—is accelerating. By 2031, 800V platforms are projected to account for approximately half of global BEV shipments, making the automotive sector the largest contributor to power SiC revenues throughout the forecast period（Source：Yole Group「Power SiC 2026 – Markets and Applications」）. In addition, unprecedented power requirements in AI data centers are mandating new power architectures, establishing AI infrastructure as a major demand driver alongside EVs, renewables, and energy storage systems （Source：Compound Semiconductor「Power SiC enters the AI age, says Yole」）.

Regarding total market size, the SiC device market is projected to grow from USD 4.02 billion in 2025 to USD 18.61 billion by 2034, registering a CAGR of 17.72% from 2026 to 2034 （Source：Fortune Business Insights「Silicon Carbide (SiC) Devices Market」Report ID: FBI112103）.

At the same time, the supply side is undergoing an adjustment phase. Following an aggressive CapEx boom between 2019 and 2024, an upstream oversupply emerged. By 2025, capacity utilization across the SiC supply chain dropped to around 50% in upstream substrate manufacturing and roughly 70% in device fabrication lines. This correction is expected to persist through 2027–2028（Source：Semiconductor Today「Power SiC faces overcapacity downturn until 2027–2028」）.

These combined market dynamics imply that in the next growth phase, competitiveness will shift from merely "being able to fabricate" to "fabricating with high yields and high throughput." The transition to more cost-effective 200 mm (8-inch) wafer platforms, along with the high-volume manufacturing of trench and superjunction MOSFETs, is expected to take center stage（Source：Semiconductor Today「Power SiC faces overcapacity downturn until 2027–2028」）. Consequently, micro-fabrication technologies capable of realizing fine, deep trench profiles and thick-film processing for high-voltage applications—especially dry etching precision and throughput—are emerging as critical process steps that directly dictate overall cost structures.

Principles of Dry Etching: What Happens Inside the Plasma?

Dry etching is a micro-fabrication technology that converts process gases into plasma, using the generated ions and radicals to etch the material surface. The driving forces behind this process fall into two main categories:

•  Chemical Reaction: Radicals in the plasma react with the material surface, forming volatile by-products that are pumped out of the chamber.

•  Physical Sputtering: Accelerated ions strike the surface, physically breaking chemical bonds.

In conventional silicon processing, process designs that strike a balance between these two mechanisms—while relying primarily on chemical reactions—have been widely established. Key parameters such as gas chemistry, pressure, plasma density, and RF bias power are all optimized under the assumption that chemical reactions proceed smoothly.

The reason standard silicon recipes fail for SiC is that this fundamental assumption no longer holds true.

For a more detailed explanation of basic dry etching principles and how they differ from wet etching, please refer to our dedicated article. Here, we will focus specifically on the challenges unique to SiC.

Four Reasons Silicon Etch Conditions Fail for SiC

Reason 1: High Si–C Bond Energy, Crystal Structure, and Hardness

Silicon carbide (SiC) exhibits extreme hardness and chemical inertness compared to silicon. The crystalline Si–C bonds are substantially stronger than Si–Si bonds, making the material far less reactive chemically.

Consequently, applying conventional silicon etch chemistries (such as standard fluorine-based gases) and standard plasma densities results in insufficient chemical reaction rates, failing to achieve practically viable etch rates.

This is not merely a matter of a slight drop in etch rate; it represents a fundamental qualitative shift where chemically dominated process designs no longer function effectively. Attempting recipe development simply by fine-tuning existing silicon recipes during the initial development phase will likely lead down the wrong optimization path.

Reason 2: High Thermal Conductivity Dissipates Reaction Energy

Another defining characteristic of SiC is its high thermal conductivity. While this offers excellent heat dissipation during device operation, it works as a disadvantage during etching processes.

Typically, local thermal energy delivered to the substrate surface by plasma irradiation helps drive surface chemical reactions. However, because SiC dissipates heat extremely rapidly, the local thermal energy required to activate these reactions quickly diffuses away. This thermal dissipation impedes processes that rely on thermal activation to break chemical bonds, resulting in etch rates significantly lower than those of silicon（Source：Semicorex「Understanding the Differences in Etching Between Silicon and SiC Wafers」(in Japanese)）.

Wafer temperature profile control becomes an independent, critical design variable in SiC processing. While cooling in silicon etching is primarily intended to prevent overheating, SiC etching introduces the added requirement of managing precisely where and how much energy is retained at the surface.

Reason 3: Excessive Ion Bombardment Erodes Masks — The Selectivity Dilemma

When chemical etching is sluggish and thermal energy dissipates quickly, the intuitive solution is to enhance physical sputtering. Indeed, standard approaches rely heavily on energetic ion bombardment within high-density plasmas to physically break bonds.

However, this creates a severe trade-off. Increasing ion bombardment via higher RF bias power aggressively sputters the patterned etch mask (such as SiO₂ or metal masks like Ni) as well. As a result, the mask may be completely consumed before reaching the target depth—leading to poor etch selectivity (defined as the SiC etch rate divided by the mask etch rate).

While it is often suggested that "simply increasing the etch rate solves the problem," the allowable bias power operating window varies drastically depending on the mask material's durability and the target depth. The deeper the required etch profile, the more essential it becomes to evaluate performance not by the raw etch rate alone, but by balancing the product of selectivity and throughput.

Reason 4: Sidewall Roughness and Profile Control Challenges

When fabricating trench-gate structures or via holes for power devices, high anisotropy (verticality) and smooth sidewalls are imperative.

However, because SiC etching relies heavily on physical sputtering, forming vertical profiles or intentionally tapered sidewalls required by specific device designs—while simultaneously maintaining smooth sidewall surfaces—presents an extremely difficult process control challenge.

Crucially, profile degradation directly degrades electrical device performance. Sidewall roughness causes localized electric field crowding under high-voltage operation, leading to increased leakage currents and reduced breakdown voltages. Profile control is therefore not merely a cosmetic objective, but a critical quality parameter directly governing production yields and long-term device reliability.

What SiC Etch Rates Mean for High-Volume Manufacturing

While the four points discussed in the previous section are often viewed purely as technical hurdles making fabrication difficult, they take on a completely different dimension when viewed through the lens of mass production.

A lower etch rate directly translates to longer processing time per wafer—in other words, reduced production line throughput. As the SiC industry navigates a period of capacity utilization adjustments and faces mounting pressure to cut manufacturing costs by shifting to 200 mm wafers (Source: Semiconductor Today、前掲), etch process duration directly impacts the return on investment (ROI) timeline for fab equipment.　Similarly, insufficient etch selectivity demands thicker masking layers, which in turn imposes tighter constraints on upstream lithography processes. Suboptimal profile control leads to electrical parameter variations, directly impairing production yield.

In SiC dry etching, etch rate, selectivity, and profile control do not exist as independent metrics; rather, they form an interdependent design puzzle where each constrains the others. This fundamental trade-off represents the single largest departure from conventional silicon processing.

Requirements for a Dedicated SiC Etch Architecture

Given the factors discussed above, SiC etching cannot be solved merely as an extension of conventional silicon processing technologies; it demands a dedicated design philosophy. Specifically, the processing architecture must be capable of advanced, independent control over the following parameters:

What is critical here is the concept of "independent control." In a system architecture where adjusting one parameter inadvertently alters another, it becomes impossible to secure the degree of freedom required to resolve the trade-offs mentioned above. While peak etch rate often captures the most attention during equipment evaluation, the actual speed of reaching mass-production conditions is determined by how well individual parameters can be decoupled and tuned during process recipe development.

Furthermore, whether process conditions established during the R&D phase can be reliably transferred and reproduced on high-volume manufacturing (HVM) tools is an indispensable consideration—especially for challenging materials like SiC, where process optimization is inherently difficult.