While the Bosch process—the de facto standard in silicon deep reactive-ion etching (Si DRIE)—is widely adopted in mass production for MEMS and TSV ( Through-Silicon Vias) , its fundamental mechanism inevitably creates periodic sidewall undulations known as scallops. With the rapid expansion of 3D packaging and fine-pitch TSV, scalloping has become a critical challenge directly impacting device reliability. 
Based on industry data, this article provides a systematic overview of the Bosch process mechanism, the physics behind scalloping, its impact on device performance, and reduction strategies along with their trade-offs against etch rates. 

Developed by Robert Bosch GmbH in Germany, the Bosch process has established itself as the de facto standard in deep silicon etching. It achieves vertical, high-aspect-ratio trenches and vias by alternately repeating two phases: 

1. An isotropic etching step using fluorine-based gases such as SF₆​ 
2. A passivation layer deposition step using fluorocarbon polymerizing gases such as C₄F₈​ 

However, this alternating etch-and-passivation mechanism inherently creates periodic ripples—scalloping—along the trench sidewalls. Because this is structurally unavoidable by design, utilizing the Bosch process requires advanced nanoscale control techniques. 

Rapid Growth of 3D Packaging and Fine-Pitch TSV

Driven by exploding demand in AI, 5G, and High-Performance Computing (HPC), 3D-IC technology—which vertically interconnects multiple dies using TSV—is seeing rapid adoption. TSV diameters and pitches continue to shrink, with next-generation designs already reaching pitches under 20 μm （Source：Mordor Intelligence）.

The overall TSV technology market is projected to expand at a rapid CAGR of 22.5% (2026–2035), with medium-diameter TSV (5–10 μm) currently representing the largest segment（Source：Global Market Insights）.

As via dimensions shrink, sub-micron scalloping accounts for a proportionally larger share of the effective via diameter and sidewall surface area. Consequently, the ability to control scalloping at the nanometer scale has become a key differentiator for market leadership.

International Quality Standardization by SEMI

The SEMI 3D Packaging & Integration Committee has published numerous TSV-related standards, including SEMI 3D1 (which defines terminology for the geometrical measurement of TSV) and SEMI 3D6 (guidelines for CMP and microbump processes). This indicates that TSV sidewall profile control has been elevated to an objective quality standard that must be complied with across the entire global supply chain（Source：SEMI Standards）.

Degraded Electrical Reliability and Increased Leakage Current

When fabricating trench MOS structures, the sharp peaks and troughs of the sidewall undulations cause local electric field concentration, leading to increased leakage current and lower breakdown voltage. Studies on silicon p-i-n diodes have also confirmed that sidewall damage caused by scalloping degrades critical device parameters, such as minority carrier lifetime and depletion layer width （Source：OSTI ）.

Void Formation and Deposition Failures in TSV Fabrication

In the TSV copper-filling process, conformal deposition of an insulation layer, a barrier layer, and a seed layer is essential. Pronounced scalloping and rough sidewalls create a "shadowing effect" during sputtering, resulting in seed layers that are extremely thin or discontinuous. This leads to voids and seams during subsequent copper electroplating, causing increased electrical resistance, interface delamination from thermal stress, and cracking（Source：Nature Scientific Reports）.

The primary factor determining scallop size in the Bosch process is the duration of the silicon etching step. Longer etch steps lead to greater isotropic lateral etching, resulting in larger scallop depths.

Theoretically, ultra-fast gas switching cycles between etching and deposition can suppress scallop growth down to the nanometer scale. However, increasing the switching frequency introduces a fundamental physical trade-off: chamber gas residence times and plasma stabilization overheads become proportionally larger, significantly reducing the net etch rate（Source：Kyoto University Research Report）.

Furthermore, continuous rapid valve actuation and high-speed plasma matching put severe mechanical stress on mass-production hardware, raising risks of frequent maintenance and costly downtime.

Across the industry, three primary technical approaches are commonly used to mitigate scalloping:

• High-Speed Bosch Process:：Achieves ultra-fast gas switching cycles to physically restrict scallop formation during the etch cycle.

• Post-Process Smoothing：Applies secondary chemical or thermal surface treatments after the standard Bosch etch to smooth away existing sidewall scallops.

• Non-Bosch / Cryogenic Etching：Avoids alternating cyclic steps altogether by utilizing alternative continuous plasma chemistries or cryogenic wafer cooling to eliminate scalloping at the root.

While effective at reducing scallops, each method relies on specialized process conditions and unique hardware configurations. As a result, they often introduce new challenges to throughput stability and equipment uptime in mass production environments.
In High-Volume Manufacturing (HVM), the ultimate goal is not merely chasing extreme single-parameter records. Instead, it demands a comprehensive capability to consistently achieve both reliable scallop control that guarantees device yield and industry-leading etch rates over extended production runs.

SPP Technologies (SPT) holds a 90% domestic market share in Japan for MEMS deep silicon etching systems, establishing itself as the industry de facto standard. Backed by years of proven performance on high-volume production lines, SPT’s expertise is built on extensive process data refined in demanding HVM environments—far beyond mere lab-scale achievements.

SPT’s Si DRIE platforms, "Predeus" and "Proxion," advanced the precision control of deposition and etch cycles within the Bosch process. This enables high verticality, minimized scalloping, and minimal critical dimension (CD) loss simultaneously—maintaining industry-leading etch rates while ensuring superior electrical and structural reliability.

Furthermore, beyond DRIE, SPT offers proprietary low-temperature PECVD systems (Cetus / Capella) designed to deposit insulating and passivation films inside TSVs under low thermal budgets. SPT’s core strength lies in delivering a seamless, end-to-end integrated solution—from forming vias with minimal scalloping to depositing high-quality, void- and crack-free dielectric layers.

In addition, SPT provides a modular architecture that seamlessly scales from a single-chamber configuration for R&D to high-volume production platforms accommodating up to four chambers. Process recipes for low scalloping and high aspect ratios established during R&D can be directly scaled up to mass production without re-tuning, significantly minimizing time-to-market for customers.

• The Bosch process is the de facto standard for Si DRIE, but inherently produces periodic sidewall scalloping due to its alternating cyclic mechanism.

• The rise of fine-pitch TSV and 3D packaging has elevated scallop control to a top-priority quality standard.

• Scalloping causes multifaceted defects, including increased leakage current and void formation during TSV metallization.

• Ultra-fast gas switching is an effective mitigation strategy, yet it presents a fundamental physical trade-off against net etch rates.

• SPP Technologies leverages its 90% Japanese MEMS market share and an integrated DRIE + Low-Temperature PECVD portfolio to deliver the optimal balance for high-volume manufacturing.