Advanced electronics such as smartphones, automotive sensors, IoT devices, autonomous-driving LiDAR, and biomedical devices rely on technologies that operate behind the scenes. One of these is Si DRIE (Silicon Deep Reactive Ion etching). The Bosch process, an industry standard, enables fast formation of deep, vertical structures in silicon, but also presents challenges such as scalloping and aspect-ratio-dependent etching (ARDE). This article provides a systematic overview of the principles of Si DRIE and the Bosch process, common industry challenges, and their role in MEMS and semiconductor manufacturing.

Si DRIE (Silicon Deep Reactive Ion Etching) is a specialized process for selectively and vertically etching fine, high-aspect-ratio structures into silicon substrates. By combining chemical reactions with plasma-based physical processes, it enables the formation of trenches, through-silicon vias (TSV), and complex cavities that conventional isotropic wet etching cannot achieve.

The rapid adoption and advancement of smartphones, sensors, IoT devices, LiDAR, photonic components for optical communications, and biomedical devices—including microfluidic devices—are driving demand for smaller, higher-performance components. Si DRIE systems are increasingly essential for manufacturing complex, three-dimensional structures with high aspect ratios.

Semiconductor fabs are accelerating the transition to dry etching, which offers greater process control and less physical and chemical damage to devices.（Source：Strategic Market Research）. As a result, the market share of wet etching is gradually declining. One study reports that the DRIE segment accounted for 43.8% of global revenue in the semiconductor dry etching systems market in 2023, strongly driving market growth（Source：Grand View Research）.

The two industry-standard approaches at the core of DRIE technology are the Bosch process and the cryogenic process.

The essence of the Bosch process lies in rapidly alternating between two processes with different characteristics. 

• Etching process: High-rate isotropic etching using gases such as sulfur hexafluoride (SF₆).

• Passivation process: Sidewall protection through polymer deposition using gases such as octafluorocyclobutane (C₄F₈).

By repeatedly alternating between “etching” and “protection,” anisotropic deep etching is achieved. This suppresses lateral erosion while allowing the structure to be etched primarily in the vertical direction.

The Bosch process offers a high etch rate, high selectivity to photoresist and oxide films, and excellent anisotropy. It is generally used to fabricate structures with feature sizes of 1 µm or larger and depths exceeding 10 µm. 

Another major technique is cryogenic deep silicon etching (Cryo-DSiE), in which the substrate is maintained at an extremely low temperature, typically between −80°C and −120°C, during processing. It is mainly used to create smooth sidewalls, perform nanoscale etching at approximately the 10 nm level, and form tapered profiles in applications such as micromolds. 

As the industry standard, the Bosch process involves inherent, structural trade-offs based on its fundamental principles. Below are the three key challenges that MEMS designers and process engineers inevitably face:

Challenge 1: Sidewall Scalloping (Wavy Profile Formation)

In the Bosch process, as a side effect of the alternating etching and passivation mechanism, microscopic undulations (scallops) are formed on the trench sidewalls with each etching cycle. In optical devices, high-frequency (RF) devices, and microfluidic devices requiring laminar flow, this sidewall roughness can cause fatal performance degradation and energy loss.

Challenge 2: Aspect Ratio Dependent Etching (ARDE / RIE-lag)

Aspect Ratio Dependent Etching (ARDE), also known as "RIE-lag," is a physical constraint where the etch rate decreases significantly as the aspect ratio of the feature increases（Source：Google Patents JP2008504975A）. As a concrete example, an experiment simultaneously etching trenches ranging from 2.5 µm to 100 µm in width on the same substrate reported significant depth variations as follows:

• 100 µm-wide trench: Reached a depth of 130 µm

• 10 µm-wide trench: Limited to a depth of 94 µm

• 2.5 µm-wide trench: Reached only a depth of 62 µm

This is not merely due to gas starvation; it is caused by a complex combination of multiple mechanisms, including the physical loss of ion flux at the bottom of the etched substrate, neutral shadowing effects, and the depletion of reactive neutral species due to Knudsen transport. In the fabrication of MEMS devices where diverse lateral dimensions coexist, addressing ARDE is an unavoidable and critical challenge.

Challenge 3: Difficulty in Balancing CD Loss and Selectivity

When forming deep trenches or Through-Silicon Vias (TSV), it is critical to suppress "undercutting"—where etching progresses laterally directly beneath the mask—and to maintain the Critical Dimension (CD) as designed. At the same time, high selectivity is required to protect photoresist, SiO₂ hard masks, and other mask materials from prolonged plasma exposure. However, optimizing the process window to simultaneously satisfy a high etch rate, high selectivity, and minimized CD loss remains a significant challenge.

Si DRIE plays a core role in the mass production and manufacturing of advanced device structures, such as power MOSFETs, piezoelectric MEMS devices, inkjet printheads, LEDs, optical devices, and RF (radio-frequency) devices. In particular, TSV  formation on 200 mm and 300 mm wafers—the mainstream in high-volume manufacturing lines—represents one of the primary applications for Si DRIE systems utilizing the Bosch proces.Source：Fraunhofer IZM）.

• Si DRIE is an indispensable technology for forming high-aspect-ratio microstructures in silicon, serving as a cornerstone for the manufacturing of MEMS, semiconductors, and advanced devices.

• The Bosch process is the industry standard that achieves anisotropic deep etching by rapidly alternating between SF₆ etching and C₄F₈ passivation.

• Conversely, it entails three inherent structural challenges: scalloping, ARDE, and the trade-off between CD loss and selectivity. The ability to precisely control these factors is the true hallmark of an equipment manufacturer’s technical capability.

• To balance yield and quality in high-volume manufacturing lines, holistic process control technology is essential, rather than simply optimizing individual parameters in isolation.