In high-volume manufacturing (HVM) of GaN HEMTs, surface damage induced during the plasma etching process directly dictates manufacturing yield and device performance. Because gallium nitride (GaN) is chemically inert, etching intrinsically relies on physical ion bombardment. As a consequence, even a minute subsurface damage layer can manifest as increased gate leakage current and degraded dynamic on-resistance . Tailored for engineers seeking to grasp the underlying fundamentals—why damage occurs, what degrades electrical characteristics, and which parameters must be controlled to mitigate it—this article directly addresses key process-development challenges. 

What Is a GaN HEMT? The 2DEG as a "Fragile Channel"

Structure and Operating Principles of GaN HEMTs

A GaN HEMT (High Electron Mobility Transistor) operates by utilizing a Two-Dimensional Electron Gas (2DEG) formed at the heterojunction interface between an AlGaN barrier layer and a GaN channel layer. This interface, where electrons can travel at extremely high velocities, underpins the superior high-frequency response and low-loss performance of GaN HEMTs.

As a semiconductor material, GaN features a wide bandgap of 3.4 eV (compared to 1.1 eV for silicon), an exceptionally high breakdown electric field strength, and high electron mobility. These material properties translate to significantly reduced switching and conduction losses, driving widespread adoption across AI data centers, electric vehicles (EVs), 5G/6G wireless infrastructure, and fast chargers.

From a market perspective, the power GaN device market is projected to expand from $355 million in 2024 to approximately $3 billion by 2030, representing a compound annual growth rate (CAGR) of 42%（Source：Semiconductor Today）. This rapid market expansion directly heightens the demand for stringent mass-production yields.

Why Is Gallium Nitride Difficult to Etch?

GaN exhibits extreme chemical stability and robust atomic bond strength. Consequently, conventional plasma etching cannot proceed via chemical reactions alone using chlorine-based chemistries (e.g., Cl₂​ or BCl₃​). Instead, the etching process must rely heavily on physical ion bombardment—accelerating ions within the plasma to strike the substrate.

This creates a structural dilemma inherent to GaN processing: the very driving force that enables etching is itself the fundamental root cause of crystal damage. Etch rate and low-damage processing inevitably present themselves as a direct, competing trade-off.

Principles of Plasma Etching and the Processing Dilemma in GaN

Classification of Plasma Etching and the Role of Ion Energy

Plasma etching fundamentally relies on a combination of chemical reactions driven by reactive gases and physical effects induced by incident ions. High-density plasma systems, such as Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE), allow for the independent control of plasma generation and substrate ion extraction (bias). This decoupled control enables practical etch rates even for difficult-to-etch materials like GaN.

From an engineering perspective, the critical factor is that this bias power—which governs ion energy—simultaneously dictates both the physical morphology and the resulting electrical performance. While standard practice suggests that "increasing bias power increases the etch rate," in GaN HEMT processing, every increment in bias power directly escalates the risk of device degradation. Even if two features achieve identical critical dimensions (CD) and etch depths, their electrical characteristics can end up entirely different.

How Surface Damage Degrades HEMT Characteristics

Crystal Lattice Disruption and Nitrogen Vacancy Formation

Physical ion bombardment disrupts the crystal lattice at the GaN surface and subsurface, generating nitrogen vacancies and lattice defects. Crucially, this damage occurs on a scale imperceptible through optical microscopy or cross-sectional scanning electron microscopy (SEM). A textbook pitfall in this process is when etched features match target dimensions perfectly, yet critical issues only emerge during subsequent electrical characterization. 

Increased Leakage Current (Lowering of Schottky Barrier Height)

Empirical data confirms that increasing bias power (ion energy) systematically decreases the Schottky barrier height (ΦB​) of GaN contacts, leading to an increase in reverse leakage current. Notably, these specific findings originated from research on vertical trench-gate MOSFETs, where Schottky barrier diode evaluations were conducted as part of trench structure verification. When extrapolating these quantitative trends to lateral GaN HEMTs with 2DEG channels, differences in device architecture must be taken into account. 

This indicates that etch damage is not a binary ("present or absent") phenomenon; rather, it scales continuously with ion impact energy, directly impacting electrical performance. From an engineering standpoint, "low-damage processing" should not be viewed as eliminating damage entirely, but rather as constraining damage levels within a permissible threshold that preserves target device specifications.

2DEG Degradation, Dynamic On-Resistance, and Current Collapse

Etch-induced damage sharply increases the sheet resistance (Rsheet of the 2DEG channel, triggering catastrophic performance degradations such as elevated dynamic on-resistance and current collapse during high-frequency switching operations （Source：Kozak, J. P. 他「Stability, Reliability, and Robustness of GaN Power Devices: A Review」IEEE Transactions on Power Electronics, 2023, Vol.38, No.7, pp.8442-8471）.

In other words, the detrimental effects of surface damage extend far beyond static electrical degradation. They manifest most acutely under dynamic switching conditions—precisely the operational domain where GaN devices deliver their core value. Establishing process recipes solely based on static characterization risks severe yield instability and dynamic performance variation during high-volume manufacturing.

Furthermore, dynamic characterization methodologies and reliability testing protocols for GaN power devices are actively being standardized by the JEDEC JC-70 committee（Source：Kozak, J. P. 他「Stability, Reliability, and Robustness of GaN Power Devices: A Review」IEEE Transactions on Power Electronics, 2023, Vol.38, No.7, pp.8442-8471）. As industry standards solidify around these dynamic metrics, process engineers will face increasingly stringent requirements to demonstrate accountable, well-controlled damage mitigation strategies.

Processing Precision Required for Normally-Off (E-mode) GaN HEMTs

In power electronics applications, normally-off operation (enhancement-mode: E-mode)—where no current flows at zero gate bias—is an essential requirement from a fail-safe standpoint. Typical architectures employed to achieve this include p-GaN gate structures and recessed-gate structures that leave an ultra-thin AlGaN barrier layer.

These processes demand exceptionally stringent selectivity and uniformity: they require either completely removing the p-GaN cap layer without damaging the underlying active layer, or precisely etching the thin AlGaN barrier to leave an exact target thickness. With conventional continuous-wave plasma etching, maintaining depth control and across-wafer uniformity at the nanoscale has proven technically challenging（Source：Plasma atomic layer etching of GaN/AlGaN materials and application: An overview）。

As the remaining film thickness decreases, any given absolute depth of damage accounts for a proportionally larger fraction of the critical layer. For this reason, low-damage etching in E-mode architectures is not merely a yield-enhancement measure, but a fundamental prerequisite for device viability.

Two Approaches to Low-Damage Processing

Currently, industry approaches to minimizing etching damage can be broadly categorized into two main paradigms:

Approach 1: Cyclic Processing (Atomic Layer Etching)

Atomic Layer Etching (ALE) is a technique that temporally separates the etch sequence into two distinct steps: "surface modification" and "removal." First, the GaN surface is modified using a chlorine-based chemistry; following a purge of the residual gas, the modified layer alone is physically desorbed using low-energy noble gas plasma, such as argon （Source：Plasma atomic layer etching of GaN/AlGaN materials and application: An overview）.

This self-limiting reaction mechanism enables atomic-scale depth control while keeping ion energy at a minimum. However, it should be noted that the etch-per-cycle (EPC) varies substantially depending on the gas chemistry and process parameters, with reported values spanning a wide range from 0.15 to 1.85 nm/cycle（Source：Issue 11 - Volume 43 - Journal of Semiconductors - IOPscience ）.For instance, in an experiment selectively removing a GaN layer over AlGaN using a BCl₃​/Ar chemistry, the process completed in 135 cycles, yielding an estimated EPC of 0.74 nm/cycle （Source：Tang & Liu「Removal of GaN film over AlGaN with inductively coupled BCl3/Ar atomic layer etch」Chinese Physics B 31, 018101 (2022)）. It must be emphasized that this is an estimated figure from a specific experimental setup and not representative of ALE processes as a whole.

Conversely, this approach entails inherent throughput constraints. Because etching several tens of nanometers requires hundreds of cycles, the overall etch rate is significantly lower than that of conventional RIE. Maintaining adequate wafer throughput on high-volume production lines—and thereby optimizing the Cost of Ownership (CoO)—presents a substantial challenge（Source：Atomic layer etching of GaN using Cl2 and He or Ar plasma）。

Approach 2: Low Ion-Energy Control in Continuous-Wave Processing

The alternative strategy involves maintaining a continuous-wave (CW) RIE regime while reducing the incident ion energy itself to the lowest controllable limit.

As previously discussed, etch damage scales continuously with bias power. In other words, if output power can be stably and precisely regulated down to the low-RF-power regime, damage levels can be maintained beneath device-degradation thresholds without relying on cyclic schemes. SPP Technologies' RIE platform integrates dedicated RF power supplies engineered for high-precision delivery even in extremely low RF power ranges, thereby mitigating physical damage within a continuous-wave RIE process.

Nevertheless, this approach is not a universal solution for every process step. Depending on the required remaining-film precision and specific material systems, the self-limiting nature of cyclic processing remains advantageous in certain applications. In practice, the most viable engineering strategy is to evaluate each step based on the target layer structure and throughput requirements, determining the optimal etching methodology on a process-by-process basis.

Tool-Level Requirements Supporting Low-Damage Processing

The architecture and control systems of a plasma etching tool directly determine the success of damage mitigation. When targeting high-volume manufacturing (HVM) of GaN HEMTs, tool platforms must satisfy at least the following key requirements:

• Output Control Precision in the Low-RF-Power Regime:While simply reducing bias power is straightforward, maintaining stable and repeatable power delivery in extremely low-power regimes presents a distinct engineering challenge. The lower boundary of a usable process window is fundamentally governed by the RF power supply’s precision control capabilities.

• Dual Compatibility with Fluorine- and Chlorine-Based Chemistries:In realistic device integration flows, processes require not only etching GaN and AlGaN layers (primarily chlorine-based chemistries) but also patterning passivation layers and interlayer dielectrics such as SiN and SiO₂ (primarily fluorine-based chemistries). Overall device yield depends on the integrity of the entire stack, not just the active layers.

• Scalability from R&D to High-Volume Manufacturing:The ability to transfer low-damage recipes developed during R&D directly to high-volume production lines—without altering core chamber architecture—is a decisive factor in time-to-market. SPP Technologies offers a scalable platform portfolio ranging from standalone single-chamber modules for R&D to multi-chamber cluster configurations integrated with vacuum transfer robots for production.

• 200 mm Wafer Compatibility:Driven by the need to reduce manufacturing costs and improve gross die per wafer, capital investments transitioning from 6-inch to 8-inch (200 mm) wafer diameters are accelerating across the industry（Source：Semiconductor Today）. This scaling up in wafer size simultaneously raises the bar for across-wafer process uniformity.

Summary

Key Considerations in GaN HEMT Dry Etching:

Need Advanced Damage Control for Your GaN Fabrication?

Backing our solutions with 30+ years of Si-DRIE leadership, SPP Technologies provides cutting-edge plasma etch equipment for compound semiconductors. Supporting both F- and Cl-based chemistries with fine-tuned low-RF-power control, we enable ultra-low-damage GaN active-layer etching alongside robust dielectric/hard-mask processing.

Key Use Cases & Consultations:

• Minimizing lattice damage in existing production recipes

• Scaling R&D processes to 200 mm volume manufacturing

• Co-optimizing etch parameters for advanced GaN HEMT heterostructures

Contact our process experts today or request technical white papers to learn more.